Cadence Design Systems, Inc. has announced the first LPDDR5X memory interface IP design optimized to operate at 8533Mbps. Available now for customer engagements, the Cadence® LPDDR5X IP boasts a new high-performance, scalable and adaptable architecture based on Cadence’s proven and highly successful LPDDR5 and GDDR6 product lines. The new Cadence LPDDR5X memory IP solution consists of a silicon-proven PHY and high-performance controller designed to connect to LPDDR5X DRAM devices that follow the JEDEC JESD209-5B standard. The controller/PHY interface is based on the latest DFI 5.1 specification, and a variety of on-chip buses are supported.
LPDDR5X memory opens up a wide variety of high-bandwidth applications beyond the mobile market traditionally served by LPDDR memory, including advanced driver assistance systems (ADAS), autonomous driving, lower-end edge AI and networking. Cadence LPDDR5X IP is designed to enable the industry’s next-generation SoC designs for these and other applications with flexible floorplan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements.
Cadence design IP supports the fastest data rate defined by the JEDEC standard (JESD209-5B). Cadence’s LPDDR5X Controller and PHY have been verified with Cadence’s Verification IP (VIP) for LPDDR5X to provide rapid IP and SoC verification closure. Cadence VIP for LPDDR5X includes a complete solution from IP to system-level verification with DFI VIP, LPDDR5X memory model and System Performance Analyzer.
The LPDDR5X IP supports Cadence’s Intelligent System Design™ strategy, which enables SoC design excellence with high-performance, design-optimized, best-in-class technology.
